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<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
</ul>
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<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>G:\GWIN_soft\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picorv32.v<br>
G:\GWIN_soft\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc.v<br>
G:\GWIN_soft\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\advspi.v<br>
G:\GWIN_soft\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\ahb_bus.v<br>
G:\GWIN_soft\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_dtcm.v<br>
G:\GWIN_soft\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_itcm.v<br>
G:\GWIN_soft\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_bus.v<br>
G:\GWIN_soft\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_brancher.v<br>
G:\GWIN_soft\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbgpio.v<br>
G:\GWIN_soft\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbi2c.v<br>
G:\GWIN_soft\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbspi.v<br>
G:\GWIN_soft\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbuart.v<br>
G:\GWIN_soft\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\simpleuart.v<br>
G:\GWIN_soft\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\dm.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>GowinSynthesis V1.9.8.07</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Sun Nov 20 04:33:10 2022
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>Gowin_PicoRV32_Top</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 70.070MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.091s, Peak memory usage = 70.070MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.633s, Peak memory usage = 70.070MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.252s, Peak memory usage = 70.070MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.656s, Elapsed time = 0h 0m 0.643s, Peak memory usage = 70.070MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.236s, Peak memory usage = 70.070MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 70.070MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.066s, Peak memory usage = 70.070MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 70.070MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0.812s, Elapsed time = 0h 0m 0.825s, Peak memory usage = 70.070MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.226s, Peak memory usage = 70.070MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.345s, Peak memory usage = 70.070MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 27s, Elapsed time = 0h 0m 27s, Peak memory usage = 78.848MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.828s, Elapsed time = 0h 0m 0.858s, Peak memory usage = 78.848MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.593s, Elapsed time = 0h 0m 0.627s, Peak memory usage = 86.047MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 32s, Elapsed time = 0h 0m 32s, Peak memory usage = 86.047MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>129</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>115</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>39</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>76</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>3494</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFF</td>
<td>208</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFE</td>
<td>1809</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFS</td>
<td>20</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFSE</td>
<td>71</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFR</td>
<td>140</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFRE</td>
<td>542</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFC</td>
<td>55</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFCE</td>
<td>627</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFN</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFNR</td>
<td>15</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFNPE</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFNC</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFNCE</td>
<td>4</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>4959</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>311</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>1725</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>2923</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>528</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>528</td>
</tr>
<tr>
<td class="label"><b>SSRAM </b></td>
<td>8</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspRAM16SDP4</td>
<td>8</td>
</tr>
<tr>
<td class="label"><b>INV </b></td>
<td>16</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspINV</td>
<td>16</td>
</tr>
<tr>
<td class="label"><b>DSP </b></td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspMULT36X36</td>
<td>1</td>
</tr>
<tr>
<td class="label"><b>BSRAM </b></td>
<td>8</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSDPB</td>
<td>8</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>5551(4975 LUTs, 528 ALUs, 8 SSRAMs) / 20736</td>
<td>27%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>3494 / 16173</td>
<td>22%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 16173</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>3494 / 16173</td>
<td>22%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>8 / 46</td>
<td>17%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>clk_in</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>clk_in_ibuf/I </td>
</tr>
<tr>
<td>jtag_TCK</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>jtag_TCK_ibuf/I </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>No.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>clk_in</td>
<td>100.0(MHz)</td>
<td>66.3(MHz)</td>
<td>11</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>jtag_TCK</td>
<td>100.0(MHz)</td>
<td>116.7(MHz)</td>
<td>6</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.492</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>14.320</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>core/mem_addr_27_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>core/mem_rdata_q_13_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_in[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_in[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk_in</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_in_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>3335</td>
<td>clk_in_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>core/mem_addr_27_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>core/mem_addr_27_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>itcm_valid_s3/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>13</td>
<td>itcm_valid_s3/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>itcm_valid_s4/I3</td>
</tr>
<tr>
<td>2.495</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>itcm_valid_s4/F</td>
</tr>
<tr>
<td>2.732</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_dm2dtm_cdc_tx/vld_set_s4/I0</td>
</tr>
<tr>
<td>3.249</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>u_dm/u_dm2dtm_cdc_tx/vld_set_s4/F</td>
</tr>
<tr>
<td>3.486</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I1</td>
</tr>
<tr>
<td>4.041</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>41</td>
<td>u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F</td>
</tr>
<tr>
<td>4.278</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/ram_addr_2_s2/I3</td>
</tr>
<tr>
<td>4.648</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>70</td>
<td>u_dm/ram_addr_2_s2/F</td>
</tr>
<tr>
<td>4.885</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/ram_addr_0_s0/I2</td>
</tr>
<tr>
<td>5.339</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>103</td>
<td>u_dm/ram_addr_0_s0/F</td>
</tr>
<tr>
<td>5.576</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_29_s2/I2</td>
</tr>
<tr>
<td>6.029</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_29_s2/F</td>
</tr>
<tr>
<td>6.266</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_29_s0/I0</td>
</tr>
<tr>
<td>6.369</td>
<td>0.103</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_29_s0/O</td>
</tr>
<tr>
<td>6.606</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_29_s/I0</td>
</tr>
<tr>
<td>6.709</td>
<td>0.103</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_29_s/O</td>
</tr>
<tr>
<td>6.946</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem_rdata_29_s9/I3</td>
</tr>
<tr>
<td>7.317</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem_rdata_29_s9/F</td>
</tr>
<tr>
<td>7.554</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem_rdata_29_s5/I0</td>
</tr>
<tr>
<td>8.071</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem_rdata_29_s5/F</td>
</tr>
<tr>
<td>8.308</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem_rdata_29_s2/I2</td>
</tr>
<tr>
<td>8.761</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>mem_rdata_29_s2/F</td>
</tr>
<tr>
<td>8.998</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n5753_s3/I1</td>
</tr>
<tr>
<td>9.553</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>core/n5753_s3/F</td>
</tr>
<tr>
<td>9.790</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n5753_s1/I1</td>
</tr>
<tr>
<td>10.345</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>38</td>
<td>core/n5753_s1/F</td>
</tr>
<tr>
<td>10.582</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n2221_s2/I0</td>
</tr>
<tr>
<td>11.099</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>core/n2221_s2/F</td>
</tr>
<tr>
<td>11.336</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n2221_s8/I1</td>
</tr>
<tr>
<td>11.891</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core/n2221_s8/F</td>
</tr>
<tr>
<td>12.128</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n2221_s6/I1</td>
</tr>
<tr>
<td>12.683</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core/n2221_s6/F</td>
</tr>
<tr>
<td>12.920</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n2221_s3/I1</td>
</tr>
<tr>
<td>13.475</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core/n2221_s3/F</td>
</tr>
<tr>
<td>13.712</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n2221_s0/I3</td>
</tr>
<tr>
<td>14.083</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core/n2221_s0/F</td>
</tr>
<tr>
<td>14.320</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/mem_rdata_q_13_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk_in</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_in_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>3335</td>
<td>clk_in_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>core/mem_rdata_q_13_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>core/mem_rdata_q_13_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>18</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 8.485, 63.053%; route: 4.740, 35.223%; tC2Q: 0.232, 1.724%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.434</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>14.262</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>core/mem_addr_27_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>core/mem_rdata_q_24_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_in[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_in[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk_in</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_in_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>3335</td>
<td>clk_in_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>core/mem_addr_27_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>core/mem_addr_27_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>itcm_valid_s3/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>13</td>
<td>itcm_valid_s3/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>itcm_valid_s4/I3</td>
</tr>
<tr>
<td>2.495</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>itcm_valid_s4/F</td>
</tr>
<tr>
<td>2.732</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_dm2dtm_cdc_tx/vld_set_s4/I0</td>
</tr>
<tr>
<td>3.249</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>u_dm/u_dm2dtm_cdc_tx/vld_set_s4/F</td>
</tr>
<tr>
<td>3.486</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I1</td>
</tr>
<tr>
<td>4.041</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>41</td>
<td>u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F</td>
</tr>
<tr>
<td>4.278</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/ram_addr_2_s2/I3</td>
</tr>
<tr>
<td>4.648</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>70</td>
<td>u_dm/ram_addr_2_s2/F</td>
</tr>
<tr>
<td>4.885</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/ram_addr_0_s0/I2</td>
</tr>
<tr>
<td>5.339</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>103</td>
<td>u_dm/ram_addr_0_s0/F</td>
</tr>
<tr>
<td>5.576</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_24_s3/I2</td>
</tr>
<tr>
<td>6.029</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_24_s3/F</td>
</tr>
<tr>
<td>6.266</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_24_s0/I1</td>
</tr>
<tr>
<td>6.369</td>
<td>0.103</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_24_s0/O</td>
</tr>
<tr>
<td>6.606</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_24_s/I0</td>
</tr>
<tr>
<td>6.709</td>
<td>0.103</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_24_s/O</td>
</tr>
<tr>
<td>6.946</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem_rdata_24_s10/I3</td>
</tr>
<tr>
<td>7.317</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem_rdata_24_s10/F</td>
</tr>
<tr>
<td>7.554</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem_rdata_24_s5/I0</td>
</tr>
<tr>
<td>8.071</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem_rdata_24_s5/F</td>
</tr>
<tr>
<td>8.308</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem_rdata_24_s1/I2</td>
</tr>
<tr>
<td>8.761</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>mem_rdata_24_s1/F</td>
</tr>
<tr>
<td>8.998</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/mem_rdata_latched_24_s3/I0</td>
</tr>
<tr>
<td>9.515</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>core/mem_rdata_latched_24_s3/F</td>
</tr>
<tr>
<td>9.752</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n2226_s5/I0</td>
</tr>
<tr>
<td>10.269</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>core/n2226_s5/F</td>
</tr>
<tr>
<td>10.506</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n5359_s4/I2</td>
</tr>
<tr>
<td>10.959</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core/n5359_s4/F</td>
</tr>
<tr>
<td>11.196</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n5359_s1/I2</td>
</tr>
<tr>
<td>11.649</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>10</td>
<td>core/n5359_s1/F</td>
</tr>
<tr>
<td>11.886</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n2210_s6/I1</td>
</tr>
<tr>
<td>12.441</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>core/n2210_s6/F</td>
</tr>
<tr>
<td>12.678</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n2210_s2/I1</td>
</tr>
<tr>
<td>13.233</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core/n2210_s2/F</td>
</tr>
<tr>
<td>13.470</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n2210_s0/I1</td>
</tr>
<tr>
<td>14.025</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core/n2210_s0/F</td>
</tr>
<tr>
<td>14.262</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/mem_rdata_q_24_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk_in</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_in_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>3335</td>
<td>clk_in_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>core/mem_rdata_q_24_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>core/mem_rdata_q_24_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>18</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 8.427, 62.893%; route: 4.740, 35.376%; tC2Q: 0.232, 1.731%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.396</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>14.224</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>core/mem_addr_27_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>core/mem_rdata_q_25_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_in[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_in[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk_in</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_in_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>3335</td>
<td>clk_in_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>core/mem_addr_27_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>core/mem_addr_27_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>itcm_valid_s3/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>13</td>
<td>itcm_valid_s3/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>itcm_valid_s4/I3</td>
</tr>
<tr>
<td>2.495</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>itcm_valid_s4/F</td>
</tr>
<tr>
<td>2.732</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_dm2dtm_cdc_tx/vld_set_s4/I0</td>
</tr>
<tr>
<td>3.249</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>u_dm/u_dm2dtm_cdc_tx/vld_set_s4/F</td>
</tr>
<tr>
<td>3.486</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I1</td>
</tr>
<tr>
<td>4.041</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>41</td>
<td>u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F</td>
</tr>
<tr>
<td>4.278</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/ram_addr_2_s2/I3</td>
</tr>
<tr>
<td>4.648</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>70</td>
<td>u_dm/ram_addr_2_s2/F</td>
</tr>
<tr>
<td>4.885</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/ram_addr_0_s0/I2</td>
</tr>
<tr>
<td>5.339</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>103</td>
<td>u_dm/ram_addr_0_s0/F</td>
</tr>
<tr>
<td>5.576</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_24_s3/I2</td>
</tr>
<tr>
<td>6.029</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_24_s3/F</td>
</tr>
<tr>
<td>6.266</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_24_s0/I1</td>
</tr>
<tr>
<td>6.369</td>
<td>0.103</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_24_s0/O</td>
</tr>
<tr>
<td>6.606</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_24_s/I0</td>
</tr>
<tr>
<td>6.709</td>
<td>0.103</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_24_s/O</td>
</tr>
<tr>
<td>6.946</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem_rdata_24_s10/I3</td>
</tr>
<tr>
<td>7.317</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem_rdata_24_s10/F</td>
</tr>
<tr>
<td>7.554</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem_rdata_24_s5/I0</td>
</tr>
<tr>
<td>8.071</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem_rdata_24_s5/F</td>
</tr>
<tr>
<td>8.308</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem_rdata_24_s1/I2</td>
</tr>
<tr>
<td>8.761</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>mem_rdata_24_s1/F</td>
</tr>
<tr>
<td>8.998</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/mem_rdata_latched_24_s3/I0</td>
</tr>
<tr>
<td>9.515</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>core/mem_rdata_latched_24_s3/F</td>
</tr>
<tr>
<td>9.752</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n2226_s5/I0</td>
</tr>
<tr>
<td>10.269</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>core/n2226_s5/F</td>
</tr>
<tr>
<td>10.506</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n2220_s10/I2</td>
</tr>
<tr>
<td>10.959</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core/n2220_s10/F</td>
</tr>
<tr>
<td>11.196</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n2220_s5/I2</td>
</tr>
<tr>
<td>11.649</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>14</td>
<td>core/n2220_s5/F</td>
</tr>
<tr>
<td>11.886</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n2209_s4/I1</td>
</tr>
<tr>
<td>12.441</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core/n2209_s4/F</td>
</tr>
<tr>
<td>12.678</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n2209_s1/I1</td>
</tr>
<tr>
<td>13.233</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core/n2209_s1/F</td>
</tr>
<tr>
<td>13.470</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n2209_s16/I0</td>
</tr>
<tr>
<td>13.987</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core/n2209_s16/F</td>
</tr>
<tr>
<td>14.224</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/mem_rdata_q_25_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk_in</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_in_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>3335</td>
<td>clk_in_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>core/mem_rdata_q_25_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>core/mem_rdata_q_25_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>18</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 8.389, 62.788%; route: 4.740, 35.476%; tC2Q: 0.232, 1.736%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.396</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>14.224</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>core/mem_addr_27_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>core/mem_rdata_q_26_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_in[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_in[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk_in</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_in_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>3335</td>
<td>clk_in_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>core/mem_addr_27_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>core/mem_addr_27_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>itcm_valid_s3/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>13</td>
<td>itcm_valid_s3/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>itcm_valid_s4/I3</td>
</tr>
<tr>
<td>2.495</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>itcm_valid_s4/F</td>
</tr>
<tr>
<td>2.732</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_dm2dtm_cdc_tx/vld_set_s4/I0</td>
</tr>
<tr>
<td>3.249</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>u_dm/u_dm2dtm_cdc_tx/vld_set_s4/F</td>
</tr>
<tr>
<td>3.486</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I1</td>
</tr>
<tr>
<td>4.041</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>41</td>
<td>u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F</td>
</tr>
<tr>
<td>4.278</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/ram_addr_2_s2/I3</td>
</tr>
<tr>
<td>4.648</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>70</td>
<td>u_dm/ram_addr_2_s2/F</td>
</tr>
<tr>
<td>4.885</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/ram_addr_0_s0/I2</td>
</tr>
<tr>
<td>5.339</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>103</td>
<td>u_dm/ram_addr_0_s0/F</td>
</tr>
<tr>
<td>5.576</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_24_s4/I2</td>
</tr>
<tr>
<td>6.029</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_24_s4/F</td>
</tr>
<tr>
<td>6.266</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_24_s1/I0</td>
</tr>
<tr>
<td>6.369</td>
<td>0.103</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_24_s1/O</td>
</tr>
<tr>
<td>6.606</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_24_s/I1</td>
</tr>
<tr>
<td>6.709</td>
<td>0.103</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_24_s/O</td>
</tr>
<tr>
<td>6.946</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem_rdata_24_s10/I3</td>
</tr>
<tr>
<td>7.317</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem_rdata_24_s10/F</td>
</tr>
<tr>
<td>7.554</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem_rdata_24_s5/I0</td>
</tr>
<tr>
<td>8.071</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem_rdata_24_s5/F</td>
</tr>
<tr>
<td>8.308</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem_rdata_24_s1/I2</td>
</tr>
<tr>
<td>8.761</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>mem_rdata_24_s1/F</td>
</tr>
<tr>
<td>8.998</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/mem_rdata_latched_24_s3/I0</td>
</tr>
<tr>
<td>9.515</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>core/mem_rdata_latched_24_s3/F</td>
</tr>
<tr>
<td>9.752</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n2226_s5/I0</td>
</tr>
<tr>
<td>10.269</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>core/n2226_s5/F</td>
</tr>
<tr>
<td>10.506</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n5359_s4/I2</td>
</tr>
<tr>
<td>10.959</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core/n5359_s4/F</td>
</tr>
<tr>
<td>11.196</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n5359_s1/I2</td>
</tr>
<tr>
<td>11.649</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>10</td>
<td>core/n5359_s1/F</td>
</tr>
<tr>
<td>11.886</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n2203_s7/I1</td>
</tr>
<tr>
<td>12.441</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>core/n2203_s7/F</td>
</tr>
<tr>
<td>12.678</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n2203_s2/I0</td>
</tr>
<tr>
<td>13.195</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>7</td>
<td>core/n2203_s2/F</td>
</tr>
<tr>
<td>13.432</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n2208_s0/I1</td>
</tr>
<tr>
<td>13.987</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core/n2208_s0/F</td>
</tr>
<tr>
<td>14.224</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/mem_rdata_q_26_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk_in</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_in_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>3335</td>
<td>clk_in_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>core/mem_rdata_q_26_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>core/mem_rdata_q_26_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>18</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 8.389, 62.788%; route: 4.740, 35.476%; tC2Q: 0.232, 1.736%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.396</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>14.224</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>core/mem_addr_27_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>core/mem_rdata_q_29_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_in[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_in[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk_in</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_in_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>3335</td>
<td>clk_in_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>core/mem_addr_27_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>core/mem_addr_27_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>itcm_valid_s3/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>13</td>
<td>itcm_valid_s3/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>itcm_valid_s4/I3</td>
</tr>
<tr>
<td>2.495</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>itcm_valid_s4/F</td>
</tr>
<tr>
<td>2.732</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_dm2dtm_cdc_tx/vld_set_s4/I0</td>
</tr>
<tr>
<td>3.249</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>u_dm/u_dm2dtm_cdc_tx/vld_set_s4/F</td>
</tr>
<tr>
<td>3.486</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I1</td>
</tr>
<tr>
<td>4.041</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>41</td>
<td>u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F</td>
</tr>
<tr>
<td>4.278</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/ram_addr_2_s2/I3</td>
</tr>
<tr>
<td>4.648</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>70</td>
<td>u_dm/ram_addr_2_s2/F</td>
</tr>
<tr>
<td>4.885</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/ram_addr_0_s0/I2</td>
</tr>
<tr>
<td>5.339</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>103</td>
<td>u_dm/ram_addr_0_s0/F</td>
</tr>
<tr>
<td>5.576</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_24_s4/I2</td>
</tr>
<tr>
<td>6.029</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_24_s4/F</td>
</tr>
<tr>
<td>6.266</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_24_s1/I0</td>
</tr>
<tr>
<td>6.369</td>
<td>0.103</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_24_s1/O</td>
</tr>
<tr>
<td>6.606</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_24_s/I1</td>
</tr>
<tr>
<td>6.709</td>
<td>0.103</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>u_dm/u_s_debug_ram/ram_dout_Z_24_s/O</td>
</tr>
<tr>
<td>6.946</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem_rdata_24_s10/I3</td>
</tr>
<tr>
<td>7.317</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem_rdata_24_s10/F</td>
</tr>
<tr>
<td>7.554</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem_rdata_24_s5/I0</td>
</tr>
<tr>
<td>8.071</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem_rdata_24_s5/F</td>
</tr>
<tr>
<td>8.308</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem_rdata_24_s1/I2</td>
</tr>
<tr>
<td>8.761</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>mem_rdata_24_s1/F</td>
</tr>
<tr>
<td>8.998</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/mem_rdata_latched_24_s3/I0</td>
</tr>
<tr>
<td>9.515</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>core/mem_rdata_latched_24_s3/F</td>
</tr>
<tr>
<td>9.752</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n2226_s5/I0</td>
</tr>
<tr>
<td>10.269</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>core/n2226_s5/F</td>
</tr>
<tr>
<td>10.506</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n5359_s4/I2</td>
</tr>
<tr>
<td>10.959</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core/n5359_s4/F</td>
</tr>
<tr>
<td>11.196</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n5359_s1/I2</td>
</tr>
<tr>
<td>11.649</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>10</td>
<td>core/n5359_s1/F</td>
</tr>
<tr>
<td>11.886</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n2203_s7/I1</td>
</tr>
<tr>
<td>12.441</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>core/n2203_s7/F</td>
</tr>
<tr>
<td>12.678</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n2203_s2/I0</td>
</tr>
<tr>
<td>13.195</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>7</td>
<td>core/n2203_s2/F</td>
</tr>
<tr>
<td>13.432</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/n2205_s0/I1</td>
</tr>
<tr>
<td>13.987</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core/n2205_s0/F</td>
</tr>
<tr>
<td>14.224</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core/mem_rdata_q_29_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk_in</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_in_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>3335</td>
<td>clk_in_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>core/mem_rdata_q_29_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>core/mem_rdata_q_29_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>18</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 8.389, 62.788%; route: 4.740, 35.476%; tC2Q: 0.232, 1.736%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
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